A non-volatile semiconductor memory cell which employs a field effect transistor which further employs a ferroelectric material, such as lead zirconate titanate (Pb(Zr.sub.0.52 Ti.sub.0.45)O.sub.3) and bismuth titanate (Bi.sub.4 Ti.sub.3 O.sub.12), as the material for the gate insulator layer, is available in the prior art. The field effect transistor has a metal-ferroelectricsemiconductor (MFS) structure. Since a ferroelectric material has a large amount of remanent polarization, a field effect transistor having a gate insulator of a ferroelectric material has a memory function. In other words, once a positive voltage is applied to the gate electrode of an n-channel metal-ferroelectric-semiconductor (MFS) field effect transistor, polarization remains in the gate insulator made of a ferroelectric material even after the voltage is removed, due to the phenomenon of remanent polarization. As a result, an n-channel is memorized along the surface of the semiconductor layer. The memorized n-channel can readily be read out by applying a voltage across the n-channel or between a source and a drain. The memorized information can readily be erased by application of a negative voltage to the gate electrode of the n-channel MFS field effect transistor. When the MFS field effect transistor is a p-channel transistor, the polarity of the voltage to be applied to the gate electrode of the field effect transistor should be reversed to a negative voltage. In this manner, binary information which can be represented by existence or nonexistence of a drain current flowing in the MFS field effect transistor can be memorized in an MFS field effect transistor.
Since an MFS field effect transistor is involved with some problems, e.g. the difficulty of depositing a ferroelectric layer directly on a silicon substrate, formation of an unnecessary silicon dioxide layer during a thermal treatment and the like, however, a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) field effect transistor was developed (ISSCC 95 February 1995 A Single-Transistor Ferroelectric Memory Cell T. Nakamura et al.).
The gate of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) field effect transistor is a series circuit of 2 capacitors including an upper capacitor consisting of an upper metal layer, a ferroelectric layer and a lower metal layer, and a lower capacitor consisting of the lower metal layer, an insulator layer and a semiconductor layer. The voltage applied to the gate is divided into two including the first voltage portion applied to the upper capacitor and the second voltage portion applied to the lower capacitor. Since the dielectric constant of a ferroelectric material is much larger than that of the ordinary insulator e.g. silicon dioxide, the capacity of the upper capacitor is much larger than that of the lower capacitor, resulting in a less amount of the first voltage portion and a larger amount of the second voltage portion. As a result, the intensity of the electric field becomes less in the ferroelectric layer, resulting in a less magnitude of remanent polarization in the ferroelectric layer. This causes malfunction for the non-volatile semiconductor memory cell.
An attempt to make the remanent polarization in the ferroelectric layer sufficiently large, is resultantly accompanied by a requirement to make the voltage to be applied to the second capacitor larger. As a result, the amount of the voltage to be applied between the gate electrode and the semiconductor layer or substrate is required to be larger. This causes a possibility of breakdown of the lower capacitor.
In conclusion, a non-volatile semiconductor memory cell employing a MFMIS field effect transistor is involved with a drawback in which a higher voltage is required for writing information therein.